A certain minimum data valid time for the data-out signal of a memory array system is necessary in each such system to obtain a window for recognizing the data coming from the array. Two approaches have been utilized in the prior art to achieve this goal. One approach shown in FIG. 1 is to extend the clock active time as long as necessary to obtain a proper data-out pulse. Extending the clock active time results automatically in a longer cycle time as shown in FIG. 1. Of course, as shown by the Data Out pulses in FIG. 1, the time during which data is valid is also extended. This approach is normally unacceptable since it obviously increases the overall machine cycle time.
A second commonly used approach is to introduce a latch into the memory array data-out path as shown in FIG. 2. The use of the serially disposed latch, of course, introduces a delay. In the arrangement of FIG. 2, an output from a Sense-Read Amplifier sets a Latch in response to a Set input and holds that level until a Reset signal is applied. The data-valid time at the input of the Data Out Driver is, therefore, a function of the set and reset times arid the amount of time the latch takes to provide an output. An example of a circuit utilizing a cascaded data latch is shown in an article entitled "Increased Valid-Data Readout Time in Static RAM" by J. A. Lawrence in IBM Technical Disclosure Bulletin, Vol. 25, No. 6, November 1982, page 2865. In the arrangement of the article, a second, cascaded output latch is utilized to increase the data-valid time. The addition of the latch causes the read data output to be valid during the entire cycle time except for a relatively small switching delay of the second latch, but the access time is impacted by the signal propagation through the latch.
It is, therefore, an object of the present invention to provide a circuit which increases the data valid time of a read signal without increasing either the access or cycle time of a memory array.
Another object is to provide a circuit in which delays due to serially disposed circuit elements between a sense/read amplifier and a data out driver are eliminated.
Still another object is to provide a circuit arrangement wherein a read/sense signal and a latch output signal are overlapped to provide a long data valid time without increasing access or cycle time.
Yet another object is to provide a circuit arrangement wherein the time during which data is valid is extended by using a portion off the next clock cycle during which another read or write signal may be present.